The disclosure herein relates to an electronic interconnect device, also known as an interposer device, used for interfacing densely populated devices such as semiconductor chips or chip scale packages to each other, or to loosely populated electronics devices such as printed circuit boards.
An interposer device can transform a fine pitch I/O (input/output) footprint to a coarse pitch I/O footprint. There are various reasons for such a transformation. The main board manufacturers do not have the capability to route conductors very close to each other, either because of the technological limitations at their factory or cost issues. There is also a reliability issue: the thermal expansion mismatch between different semiconductor devices and printed circuit boards makes the fine pitch joining extremely unreliable. Therefore the use of an interposer between semiconductor chips, such as processors, logic, ASIC and memory chips, and printed circuit boards is very common. Quite often the function of the interposer is integrated into chip packages and production sockets.
Conventionally, semiconductor components are interfaced onto a printed wiring board having a multilayer structure, where pluralities of electrical conductor layers are stacked sequentially with an insulating layer such as FR4 in between. The electrical continuity between each conductor layer is achieved through metallically plated vias. On each consecutive layer, the conductors are distributed a little outward until the desired coarse pitch has been reached.
One example of a typical structure can be found in U.S. Patent Application Publication Number 2007/0232090 A1 to Colgan et al. Conventionally, a build-up process is used as a technology for manufacturing a wiring board of a multilayer structure. With the use of the build-up process, a variety of multilayer wiring boards can be fabricated by varying the combination of a material (typically, a thermosetting resin) for an interlayer dielectric and using a via hole formation process.
A typical manufacturing process for a multilayer wiring board using the build-up process is to repeat, in turn, the formation of an insulating layer, the formation of a via hole in the insulating layer, and the formation of a wiring pattern on the insulating layer and also in the via hole, on both or either surface of a core substrate serving as a support base member. In such a structure, wiring layers and insulating layers can be thinly formed since the build-up process is used for their stacking, while the core substrate requires an appropriate thickness for affording the wiring board rigidity. Similarly connecting two opposite sides of the rigid or flexible electronics substrates, such as organic or inorganic substrates, requires the formation of through vias and subsequently the metallization of the formed vias.